The invention is related to LSSD storage elements and, in particular, to a method and apparatus for interfacing an LSSD storage element with a non-LSSD storage element to facilitate operation and testing of an integrated circuit that uses both types of storage methodologies.
Digital integrated circuits often include a number of storage elements such as latches and flip-flops that temporarily store logical states (e.g., HIGH or LOW) within the integrated circuit. Data from a component of the integrated circuit are received by the storage elements, latched or otherwise stored, and then outputted to the same and/or another component of the integrated circuit. It is often useful to selectively set the data stored in the storage elements, for example, in order to operate the integrated circuit from a known logical state. Similarly, it is also useful to shift an entire sequence of bits into the storage elements to test the integrated circuit. In the latter case, two or more storage elements are daisy-chained together so the output of one feeds the input of the next, and so on. Then, one of the storage elements in the chain is tapped, that is, selected as the point at which to shift in the controlled test bits. Similarly, a sequence of bits can be shifted out from the integrated circuit onto the chain and observed at the same or another storage element and compared with an expected output. This shifting is also referred to as xe2x80x9cscanning.xe2x80x9d The chain of storage elements is referred to as a xe2x80x9cscan chain.xe2x80x9d
One common type of storage element is a Muxscan storage element 10, depicted in FIG. 1A as a multiplexer MUX connected to a flip-flop FF. The multiplexer MUX has two inputs 0 and 1 which are selectable via a select input SEL, and an output O. The 0 and 1 inputs are typically connected to a data signal DATA and a scan-in signal SI, respectively, and the select input SEL is typically connected to a scan-enable signal SE. The DATA signal carries logic states from a predefined component of the integrated circuit during normal operation, and the scan-in signal SI provides logic states from, for example, a tester, for purposes of testing the integrated circuit. When the scan-enable signal SE is at logic LOW, the multiplexer MUX selects the DATA signal as the output. When the scan-enable signal SE is at logic HIGH, the multiplexer MUX selects the SI signal as the output. The output O is connected to an input D of the flip-flop FF, which also has a data output Q. In operation, upon assertion of a clock signal CLK, the flip-flop FF latches whatever data are at its input D (from either the DATA or SI signal) and outputs this data at the output Q.
FIG. 1B shows a simplified version of the Muxscan storage element 10 of FIG. 1A. The multiplexer MUX and the flip-flop FF of FIG. 1A have been combined into a single device that is functionally identical to the device shown in FIG. 1A.
Another type of storage element is the Level-Sensitive Scan Design, or LSSD, storage element. Generally, LSSD storage elements have an advantage over non-LSSD storage elements in that their operation does not depend on the exact timing of a clock signal. Instead, operation of an LSSD storage element depends solely on whether the clock signal has occurred, i.e., whether it has attained a certain, predefined voltage level, and not on when the clock signal has occurred. This insensitivity to exact timing avoids timing related problems such as clock skew and rise or fall times dependencies. However, LSSD storage elements have more stringent design requirements. For example, each latch in an LSSD storage element must have its own clock signal, and the clock signals may not overlap.
A popular type of LSSD storage element called an xe2x80x9cL2-Starxe2x80x9d is functionally depicted in FIG. 2. This storage element 20 has a master latch L1 and a slave latch L2 connected together. Both latches L1 and L2 have a set of inputs D1 and D2 which are latched by clock inputs CLK1 and CLK2, respectively. An output Q outputs the data from either the D1 or D2 input (whichever is latched last) on both latches L1 and L2. The master latch L1 outputs a master output signal QM and the slave latch L2 outputs a slave output signal QS. The input D1 of the master latch L1 is connected to a data signal DM carrying logic states from a predefined component of the integrated circuit, while the corresponding input D1 of the slave latch L2 is connected to another data signal DS. A write clock signal WCLK global to the integrated circuit is connected to the clock inputs CLK1 of both latches L1 and L2 for latching the data from the DM and DS signals. The input D2 of the master latch L1 is connected to a scan-in signal SI carrying logic states from, for example, a tester, for purposes of testing the integrated circuit, while the corresponding input D2 of the slave latch L2 is connected to the master output signal QM from the master latch L1. A master scan clock ACLK latches the data from the scan-in signal SI and a slave scan clock BCLK latches the data from the QM signal.
Operation of the LSSD storage element 20 will now be described with reference to the timing diagram of FIG. 3. During normal operation, the master latch L1 and the slave latch L2 both functions as independent storage elements. Upon assertion of the write clock WCLK, data carried by the signals DM and DS are latched by the two latches L1 and L2 and outputted as the output signals QM and QS, respectively. Note the two scan clocks ACLK and BCLK are inactive at this time, and the scan-in signal SI is in a xe2x80x9cdon""t carexe2x80x9d state.
During testing, or scan operation, the master latch L1 and the slave latch L2 operate together to form a 2-position shift register. Upon assertion of the master scan clock ACLK, the data from the scan-in signal SI is latched by the master latch L1 and outputted as the master output signal QM. This same data will then be latched by the slave latch L2 upon assertion of the slave scan clock BCLK and outputted as the slave output signal QS. Note, for proper operation of the scan function, the two scan clocks ACLK and BCLK must not overlap each other.
As can be seen from the timing diagram, the L2-Star configuration uses both latches L1 and L2 as independent storage elements during normal operation. However, during scan operation, the master latch L1 feeds the slave latch L2 and the latches are no longer independent. As such, in a scan chain made of multiple L2-Star storage elements, asserting the master scan clock ACLK first at the start of the scan operation destroys the initial data bit going into the input D2 of the slave latch L2. Likewise, asserting the slave scan clock BCLK first destroys the initial data bit going into input D2 of the following master latch L1. By way of example, say the scan-in signal SI is HIGH at the start of the scan operation while the master output signal QM is LOW. Upon assertion of the master scan clock ACLK, the HIGH from the scan-in signal SI is latched by the master latch L1 and the master output signal QM becomes HIGH, thus displacing the previous LOW before it can be latched by the slave latch L2. A similar displacement occurs at the next master latch in the scan chain if the slave scan clock BCLK is asserted first. Therefore, each scan operation would have to be executed twice, once with the master scan clock ACLK asserted first, and once with the slave scan clock BCLK asserted first, in order to capture all the data.
Moreover, because L2-Star type storage elements requires three separate clocks WCLK, ACLK and BCLK, they are generally not compatible with integrated circuits designed for Muxscan storage elements which require only one clock. In order to use both types of storage elements in the same scan chain, the integrated circuit would have to be modified to provide two additional separate, non-overlapping scan clocks.
The invention relates to a method and apparatus for interfacing an LSSD storage element with a non-LSSD storage element to facilitate operation and testing of an integrated circuit that uses both types of storage methodologies.
In general, in one embodiment, the invention is related to a method of interfacing a level-sensitive scan design storage element to a non-level-sensitive scan design storage element in an integrated circuit, the level-sensitive scan design storage element having a master latch and a slave latch. The method includes receiving a clock signal, generating separate, non-overlapping clocks for the master latch and the slave latch from the clock signal, and controlling an order of asserting the separate, non-overlapping clocks for the master latch and the slave latch.
In general, in one embodiment, the invention is related to an interface for interfacing an LSSD storage element with a non-LSSD storage element in an integrated circuit, the LSSD storage element having a master latch and a slave latch. The interface includes a test enable module, a clock generator module, and a master observe module connected to the test enable module and clock generator module. The test enable module is arranged to generate a test enable signal and the clock generator module is arranged to generate separate, non-overlapping clocks for the master latch and the slave latch. The master observe module is configured to selectively latch an initial data bit of the master latch by controlling separate, non-overlapping clocks of the master latch and the slave latch upon receipt of the tester enable signal.
In general, in one embodiment, the invention is related to a scan chain, including a non-LSSD storage element, an LSSD storage element having a master latch and a slave latch, and an interface connected between the two latches. The interface is configured to generate separate, non-overlapping clocks for the master latch and the slave latch and to control a latching order of the master latch and the slave latch.
In general, in one embodiment, the invention is related to an interface for interfacing an LSSD storage element with a non-LSSD storage element in an integrated circuit, the LSSD storage element having a master latch and a slave latch. The interface includes means for receiving a clock signal, means for generating separate, non-overlapping clocks for the master latch and the slave latch from the clock signal, and means for selectively asserting one of the separate, non-overlapping clocks for the master latch and the slave latch before the other.
In general, in one embodiment, the invention is related to an apparatus for interfacing an L2-Star storage element with a Muxscan storage element in an integrated circuit, the L2-Star storage element having a master latch and a slave latch. The apparatus includes a data lock-up module for latching data to be scanned into the integrated circuit, a test enable module for generating a tester enable signal, a clock generator module for generating a write clock and separate, non-overlapping master and slave scan clocks for the master latch and the slave latch, and a master observe module or selectively scanning an initial data bit from the master latch into the slave latch, depending on the generation of the tester enable signal, by asserting the slave scan clock before asserting the master scan clock.
Advantages of the invention include allowing LSSD storage elements to operatetogether with non-LSSD storage elements in an integrated circuit designed primarily for the non-LSSD storage elements. Other advantages of the invention will become apparent from the following description and the claims.